1. Field of the Invention
The invention relates to a method for manufacturing a mask programmable read only memory (ROM) and, more particularly, to a method which is suitable for use in the manufacturing of a ROM with an array structure in which memory cell transistors are serially arranged.
2. Description of the Prior Art
A ROM is a device which is programmed (in which information is written) in the manufacturing step and its memory cells are constructed by MIS transistors. The ROM is mainly classified into a ROM (NOR type ROM) which is constructed by a memory cell array of the parallel type and a ROM (NAND type ROM) which is constructed by a memory cell array of the serial type. The NAND type ROM comprises a plurality of MIS transistor arrays in each of which MIS transistors are serially connected and which is suitable for realization of a large capacity because it is more advantageous than the NOR type ROM with respect to integration density.
The programming of the NAND type ROM is executed by controlling a threshold voltage of the MIS transistors constructing the memory cells by implanting impurity ions (channel doping). Hitherto, the ion implantation for programming is performed in the step before or after the formation of a gate insulating film. However, the NAND type ROM which is programmed in the step before or after the formation of the gate insulating film needs a number of steps for a period of time after the execution of the programming to the completion of the ROM. Consequently, a long time is required until the programmed ROM is completely manufactured; namely, a turn around time is long.
To reduce such a turn around time, there has been proposed a NAND type ROM in which the ion implantation for programming is executed by high energy such as to penetrate a gate electrode after the gate electrode was formed. FIGS. 1 to 5 show such an example. FIG. 1 is a plan view. FIGS. 2 to 5 are cross sectional views ten along the lines II--II, III--III, IV--IV, and V--V in FIG. 1, respectively.
As shown in FIGS. 1 to 5, in the NAND type ROM, a field insulating film 102 is formed like a stripe onto the surface p-type silicon (Si) substrate 101, thereby isolating devices. When the field insulating film 102 is formed, boron (B) as a p-type impurity which has previously been ion implanted in the p-type Si substrate 101 of a portion serving as an isolating region between devices is diffused, so that a p.sup.+ -type channel stop region 103 is formed under the field insulating film 102.
A gate insulating film 104 is formed on the surface in a stripe-shaped active region surrounded by the field insulating films 102. In this case, ions of B are implanted into a channel region in the step before or after the formation of the gate insulating film 104 and the MIS transistors forming the memory cells are formed as the enhancement type.
Subsequently, word lines WL.sub.1 ', WL.sub.2 ', WL.sub.3 ', . . . which extend in the direction which crosses perpendicularly to the longitudinal direction of the stripe-shaped active region are formed. After that, a resist pattern 105 having an opening 105a is formed in a predetermined portion according to the program.
The resist pattern 105 is used as a mask and phosphorus (P) ions as n-type impurities are implanted into the channel region so as to penetrate the word lines WL.sub.1 ', WL.sub.2 ', WL.sub.3 ', . . . with a high energy (for example, about hundreds of keV). Consequently, the MIS transistor into which the P ions have been implanted through the opening 105a of the resist pattern 105 is formed as a depletion type and a desired program is executed.
In JP-A-64-46967, there has been proposed a method whereby in the NAND type ROM, all of the MOS transistors constructing the memory cells are previously formed as depletion type, and after a gate electrode was formed, the B ions are implanted into the channel region of only the selected MOS transistors so as to penetrate the gate electrode, thereby forming the selected MOS transistors as enhancement type, thereby reducing the energy for ion implantation for programming to about 200 keV.
In the conventional NAND type ROM show in FIGS. 1 to 5 mentioned above, since the P ion implantation for programming is executed by the high energy, the following problems occur. That is, in the case where the resist pattern 105 is used as a mask and the P ions are implanted by the high energy so as to penetrate the word lines WL.sub.1 ', WL.sub.2 ', WL.sub.3 ', . . . , the P ions also pierce the field insulating film 102 in the portion of the opening 105a of the resist pattern 105, so that the P ions are implanted into the lower side portion of the field insulating film 102 as shown in FIGS. 2 and 5 (the implanted P ions are shown by broken lines in FIGS. 2 to 5). Thus, an impurity concentration of the channel stop region 103 under the field insulating film 102 decreases. Accordingly, there is a problem such that a punch-through easily occurs between the memory cell into which the ion implantation has been executed for programming and the memory cell adjacent to such a memory cell.
To solve the above problems, there is considered a method whereby the opening 105a of the resist pattern 105 to specify the region into which the ion implantation for programming is executed is reduced and the ion implantation region is limited to only the region on the active region. For this purpose, an accuracy of the lithography needs to be set to about 1.5 .mu.m. However, it is actually difficult to realize such a high accuracy because of the mask alignment error or the like in the lithography process. The above method, therefore is not a practical method.